By Ashenden P. J.
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Additional info for The VHDL Cookbook
Next, an example showing how generic parameters can be used to specify a class of entities with varying structure: entity ROM is generic (width, depth : positive); port (enable : in bit; address : in bit_vector(depth–1 downto 0); data : out bit_vector(width–1 downto 0) ); end ROM; Here, the two generic constants are used to specify the number of data bits and address bits respectively for the read-only memory. Note that no default value is given for either of these constants. This means that when the entity is used as a component, actual values must be supplied for them.
Port_map_aspect ::= port map ( port_association_list ) The declarative part of the configuration declaration allows the configuration to use items from libraries and packages. The outermost block configuration in the configuration declaration defines the configuration for an architecture of the named entity. For example, in Chapter 3 we had an example of a processor entity and architecture, outlined again in Figure5-1. all for block_structure configuration items end for; end test_config; In this example, the contents of a package called processor_types in the current working library are made visible, and the block configuration refers to the architecture block_structure of the entity processor.
Then the new projected ouptut waveform is: 20ns 25ns '1' '1' When a signal assignment with multiple waveform elements is specified with intertial delay, only the first transaction uses inertial delay; the rest are treated as being transport delay transactions. 2. Processes and the Wait Statement The primary unit of behavioural description in VHDL is the process. A process is a sequential body of code which can be activated in response to changes in state. When more than one process is activated at the same 4.