By Francisco Serra-Graells
Low-Voltage CMOS Log Companding Analog layout provides in element state of the art analog circuit thoughts for the very low-voltage and low-power layout of systems-on-chip in CMOS applied sciences. The proposed method is principally according to bases: the instant Log Companding concept, and the MOSFET working within the subthreshold zone. the previous permits internal compression of the voltage dynamic-range for terribly low-voltage operation, whereas the latter is suitable with CMOS applied sciences and compatible for low-power circuits. the necessary historical past at the particular modeling of the MOS transistor for Companding is provided firstly. Following this basic method, a whole set of CMOS easy construction blocks is proposed and analyzed for a wide selection of analog sign processing. specifically, the coated components comprise: amplification and AGC, arbitrary filtering, PTAT iteration, and pulse period modulation (PDM). for every subject, a number of case experiences are thought of to illustrate the layout method. additionally, built-in examples in 1.2um and 0.35um CMOS applied sciences are said to ensure the great contract among layout equations and experimental information. The ensuing analog circuit topologies express very low-voltage (i.e. 1V) and low-power (few tenths of uA) functions. except those particular layout examples, a true business software within the box of listening to aids can be provided because the major demonstrator of all of the proposed easy construction blocks. This system-on-chip shows actual 1V operation, excessive flexibility via electronic programmability and intensely low-power intake (about 300uA together with the Class-D amplifier). As a outcome, the said ASIC can meet the requirements of an entire kin of universal listening to relief versions. In end, this ebook is addressed to either ASIC designers who can follow its contents to the synthesis of very low-power systems-on-chip in ordinary CMOS applied sciences, in addition to to the lecturers of contemporary circuit layout in digital engineering.
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Extra resources for Low-Voltage CMOS Log Companding Analog Design
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The contents of this chapter focus on the MOS device background needed to develop the analog circuit techniques presented in this work. Special attention is paid to the analytical large signal I/V model as the main tool for circuit design when implementing the Companding Theory. A specific extraction procedure is also introduced to obtain the required technological parameters either from numerical models or from experimental data. Model Requirements for Analytical Design Historically, numerical simulation has always been a bottleneck in the design of integrated circuits since it requires a proper balance between accuracy and computation time.
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