By Wai Kai Chen
Timing, reminiscence, energy dissipation, checking out, and testability are all the most important components of VLSI circuit layout. during this quantity culled from the preferred VLSI guide, specialists from around the globe supply in-depth discussions on those and similar issues. Stacked gate, embedded, and flash reminiscence all obtain exact remedy, together with their strength intake and up to date advancements in low-power thoughts. Reflecting the speedy improvement and value of systems-on-a-chip (SOCs), a complete bankruptcy is dedicated to application-specific built-in circuits (ASICs). Design-related subject matters comprise microprocessor architectures, format equipment, layout verification, testability options, and numerous CAD tools..
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Extra info for Memory, Microprocessor, and ASIC (Principles and Applications in Engineering, 7)
And Dobberpuhl, D. , The Design and Analysis of VLSI Circuits. Addison-Wesley Publishing Company, Reading, MA, 1985. 31. Uyemura, J. , Circuit Design for CMOS VLSI. Kluwer Academic Publishers, 1992. 32. Kang, S. M. , CMOS Digital Integrated Circuits: Analysis and Design. , New York, 1996. 33. Sedra, A. S. and Smith, K. , Microelectronic Circuits. , 1997. 34. , Switching and Finite Automata Theory. , 1978. 35. Mano, M. M. and Kime, C. , Logic and Computer Design Fundamentals. , 1997. 36. , Modern VLSI Design: A Systems Approach.
8 New VIA-2 programming ROM. 9 shows timing chart of each key signal and when Bit 4 is accessed, for example, only this line will be precharged during the precharge phase. However, all other bit lines are pulled down to GND by Dl transistors as shown in Fig. 4. When VIA-2 code exists like N4 and Bit 4, this line will be discharged. But if it does not exist, this line will stay at VDD level dynamically, as described during the word line active phase, which is shown in Fig. 9. 5 In order to evaluate worst-case speed, no VIA-2 coding on horizontal bit cell was used since transistor series resistance at active mode will be maximum with respect to GND.
When connection exists on all of bit lines vertically, total parasitic capacitance Cbs on the bit line by Ndiffusions and Cbg will be a maximum. Tills situation is shown in Fig. 6a. In the 8KW ROM, 256 bit cells are in the vertical direction, resulting in 256 times of cell bit line capacitance. 66 V and depends on ROM programming type such as diffusion or VIA-2. Short circuit currents in the sense amplifier circuits arc avoided by using a delayed enable signal (Sense Enable). 4. This line contains “0”s on all 256 cells and has the longest discharge time.